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e-book Foundations of Microprogramming: Architecture, Software, and Applications

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Citations Publications citing this paper. Microcoded Reconfigurable Embedded Processors J. References Publications referenced by this paper. Foundations of microprogramming : architecture, software, and applications Ashok K. Agrawala , Tomlinson Gene Rauscher. Fourth - generation software Asher Opler. The best way to design an automatic calculating machine Maurice Vincent Wilkes.

Agrawala , " Developing application oriented computer architectures on general purpose microprogrammable machines Dynamic problem oriented redefinition of computer architecture via microprogramming. Bit-slice microprogramming saves software compatibility. Emulate your MOS microprocessor with bipolar bit slices.

Microprogrammable microprocessor survey Phillip M. It may intervene, however, for addresses greater than 4K if flip-flop 35 has been set. For example, channel may carry an 8-bit word. Suitable microcommands, applied to control inputs 56 of demultiplexer , allow the transfer of the information present on channel to one of the output sets 57, 58, 59, 60, 61 and 62 connected to as many data input sets of memory 30 as are required.

The same microcommands applied to control inputs 56 are applied to some control inputs 63 of memory 30 and are allowed to select one of the six modules constituting memory The addressing of the memory position is obtained through inputs 55 connected to the outputs of status register , FIG. In the described embodiment, the read information has the following format:.

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The bits are applied through output set 64 to the control inputs of condition network 31 substantially formed by a multiplexer having 8 inputs and an output. A logical ONE is permanently applied to an input of network 31 while 7 different conditions C 1 through C 7 are applied to the other inputs. The bits are applied through output set 65 to the control inputs of condition selection network 32 substantially formed by a multiplexer having 32 inputs and an output.

A logical ONE is permanently applied to an input of network 32 while 31 different conditions C 8 through C 39 are applied to the other inputs. The bits are applied through output set 66 to the control inputs of condition selection network 33 substantially formed by a multiplexer having 32 inputs and an output. A logical ONE is permanently applied to an input of network 33 while 31 different conditions C 40 through C 71 are applied to the other inputs. The output sets of AND gate sets 70, 71 and 72 are connected to as many input sets of an OR gate set 73 whose outputs are connected through channel 46 to an input set of multiplexer 12, FIG.

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Priority network 40 is formed by an OR gate 74, by AND gates 75, 76, 77 and 78, and by two inverters 79 and OR gate 74 has its inputs connected to outputs 37, 38 and 39 of multiplexers 31, 32 and 33 respectively, and the output connected to an input of AND gate A second input of AND gate 75 is connected to lead The output of AND gate 75 is connected to lead Output 37 of multiplexer 31 is connected to an input of AND gate 76 which has a second input connected to lead It is therefore clear that when one of the conditions selected by multiplexer 31 is verified, that is, output 37 of multiplexer 31 is at logical ONE and network 40 is enabled by a logical ONE present on lead 47, signal EINTFO at logical ONE is generated on lead 44 and jump address JA1 is transferred to channel Output 38 of multiplexer 32 is connected to an input of AND gate 77 which has a second input connected to lead 47 and a third input connected to output 37 of multiplexer 31 through inverter It is therefore clear that when one of the conditions selected by multiplexer 32 is verified but none of the conditions selected by multiplexer 31 is verified, and furthermore that network 40 is enabled by a logical ONE present on lead 47, signal EINTFO at logical ONE is generated on lead 44 and jump address JA2 is transferred to channel Output 39 of multiplexer 33 is connected to an input of AND gate 78 which has input connected to lead 47, a third input connected to output 37 of multiplexer 31 through inverter 79 and a fourth input connected to output 38 of multiplexer 32 through inverter It is therefore clear that when one of the conditions selected by multiplexer 33 is verified but, at the same time none of the conditions selected by multiplexers 31 and 32 is verified, and furthermore network 40 is enabled by a logical ONE present on lead 47, signal EINTFO at logical ONE is generated on lead 44 and jump address JA3 is transferred to channel Having described a preferred embodiment of the invention, it is convenient to point out its advantages by means of some examples.

A first example relates to the firmware routine which develops absolute memory addresses starting from relative addresses. It is known that in modern data processing systems in order to free the program writing and the address settlement from the real memory positions, relative or conventional addresses are used; the data processing systems suitably process such addresses to obtain an absolute memory address from a relative address.

The computation may be performed in different ways according to the particular operative statuses of the system. In addition, together with the computation, it is necessary to perform several controls to secure that, during write operations, a memory zone exclusively devoted to read operations is not addressed and so on.

If the instruction is executive, an exception is pointed out and an exception treatment routine EXCP is performed; otherwise, the absolute address computation is performed by adding to the relative address the information contained in a register RLR0, as well as the information contained in a register P.

If the instruction is a write instruction, an exception is pointed out and an exception treatment routine is performed. In the contrary case, the absolute address is calculated. It is clear that the development by microinstructions of the above-described microprogram requires the execution of a separate microinstruction for each condition examination. In addition, the four microinstructions require four memory positions to be stored. The already described microprogrammed control unit has, on the contrary, the advantage to allow the simultaneous examination of several conditions. The only constraint to be considered during such simultaneous examination is the priority order according to which the several conditions must be verified with such an order having to correspond to the logical order according to which the examination of the conditions must occur.

It is clear that the microprogram development requires in this case a lower number of machine cycles and that the use of two auxiliary memories 21 and 30 is widely compensated by the lesser memory size occupation of control memory 3. A further advantage of the microprogrammed control unit is to allow the correction of microprogramming errors and to remedy possible faults of the control memory.

The use of static and permanent control memories is necessary to allow the start or initialization of the system. Also, such memories are more inexpensive and faster than the others. These memories have the inconvenience to be inalterable and so, if they have been programmed in a wrong way, they cannot be modified and the replacement of the components constituting the memory is required. The same inconvenience happens if, during the use, a fault occurs in particular positions of the control memory and causes the reading of wrong microinstructions.

In this case by using the described control unit, it is possible to bypass the wrong microinstructions owing to a fault or a microprogramming mistake. It is clear that a wrong microinstruction is reached in a sequential way or by means of a jump starting from one or several previous microinstructions. In such a predetermined position, a condition code to be examined will be written, which points to an always verified condition, that is to the condition "1" permanently applied to an input of multiplexer A jump address JA1 is associated with this code.

In such a memory position, a correct microinstruction will be substituted for the wrong microinstruction. This correct microinstruction will be followed in turn by a jump microinstruction which will refer to the microinstruction logically, subsequent to the wrong one which is therefore bypassed. It is clear that the previous description only relates to a preferred embodiment of the invention and that several modifications may be made without departing from the scope of the invention. For example, auxiliary memory 30 may contain a number of jump condition groups greater or less than 3 and correspondingly a number of jump address groups greater or less than 3.

The jump condition networks, the priority network 40 and the address selector 45 will be suitably modified in order to consider this fact.

In addition, the number of jump condition groups and the number of jump address groups stored in memory 30 do not necessarily have to coincide. For example, the number of jump condition groups stored in auxiliary memory 30 may be greater than the number of jump address groups, and one or several jump condition groups may recall some jump addresses contained in other machine registers when a condition is verified. In addition, it is possible to use auxiliary memory 21 and auxiliary memory 30 separately. In fact, it has been explained that the binary codes stored in memory 21 may be used both as addresses for memory 30 and codes for the generation of additional microcommands obtained through decoder The double function carried out by such codes imposes a reciprocal interdependence among additional microcommands and addresses of memory This restriction may be overcome as shown in FIG.

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The two input AND gate 90 receives to a first input the signal coming from the output of OR gate and to the second input a signal coming from an output of register This last signal corresponds, for example, to the most significant bit contained in register The two input AND gate 91 receives to one input the signal coming from the output of OR gate and to the other input through an inverter 92 the signal coming from an output of register , that is the signal corresponding to the most significant bit in inverted form. It is clear that in such a case the generation of the additional microcommands through decoder 34 and the enabling of the multiple jump network occur in a mutuallly exclusive way.

A further noteworthy consideration relates to the criteria for a relative priority group assignment of the several jump conditions. It has previously been noted that the several jump conditions are organized according to decreasing priority groups and that a jump condition belonging to a greater priority group prevails, when it is examined and verified, over a jump condition belonging to a lesser priority group which is also examined and verified. It some cases, it may be necessary to examine only a condition belonging to a lesser priority group.

Within the highest priority condition groups, this may be obtained by imposing that auxiliary memory 30 selects for examination a condition which would certainly not be verified. This involves in the microprogram design a careful and strict examination of the several machine statuses. In order to avoid this burden, it is sufficient to insert in the highest priority condition groups a condition which is never verified and corresponds to a "0" permanently applied to one of the inputs of multiplexers 31 and 32 of FIG. In the same way, as previously pointed out, a "1" may be permanently applied to one of the inputs in order to obtain the capability of an unconditioned jump.

Having shown and described a preferred embodiment of the invention, those skilled in the art will realize that many variations and modifications may be made to affect the described invention and still be within the scope of the claimed invention. Thus, many of the elements indicated above may be altered or replaced by different elements which will provide the same result and fall within the spirit of the claimed invention. It is the intention, therefore, to limit the invention only as indicated by the scope of the claims.

Effective date : Year of fee payment : 4. The reading of a microinstruction from the control memory also causes the reading of an information from the first auxiliary memory, such information being used to address the reading of the second auxiliary memory. The information read out from the second auxiliary memory specifies jump conditions JC1, JC2, JC3 to be examined and jump addresses JA1, JA2, JA3 and extends the information contained in the microinstruction read out from control memory.

Thus it is possible to associate jump or branch microinstructions to operative microinstructions and particularly multiple branch microinstructions to curtail the design time of the microprogram and the control memory size devoted to store them. A priority network 40 coupled to the second auxiliary memory determines the priority to be followed during the concurrent examination of several jump conditions and selects the jump address among several possible addresses according to the highest priority verified jump condition.

Zusammenfassung

Field of the Invention This invention relates to the microprogrammed control units used in data processing systems. Description of the Prior Art It is well known that modern data processing systems include a control unit which allows the system to interpret and execute instructions by means of suitable microprograms, the several program instructions forming the work program or programs assigned to the system.

Each one of these codes selects one among several conditions which must be examined; and b a plurality of binary codes representative of absolute jump addresses JA1, JA2 and JA3. In the described embodiment, the read information has the following format: bits first code JC1 identifying one out of 8 jump conditions, bits second code JC2 identifying one of 32 jump conditions, bits third code JC3 identifying one of 32 jump conditions, bits jump address JA1 coupled to first code JC1, bits jump address JA2 coupled to second code JC2, bits jump address JA3 coupled to third code JC3.

The bits are applied through output set 67 to the inputs of an AND gate set The bits are applied through output set 68 to the inputs of an AND gate set The bits are applied through output set 69 to the inputs of an AND gate set What is claimed is: 1. A microprogrammed control unit according to claim 1 wherein said first auxiliary memory has lesser addressable locations than said main control memory and further comprising control logical circuits, controlled by microcommands, to inhibit the outputs of said priority selection network when the address stored in said addressing register exceed the number of addressable locations of said first auxiliary memory.

A microprogrammed control unit according to claim 2 further comprising a second decoding network for additional microcommand generation, provided with inputs connected to the outputs of said auxiliary output register. A microprogrammed control unit according to claim 2 further comprising a second decoding network for additional microcommand generation, and a group of control gates, the inputs of said control gates being connected to the outputs of said auxiliary output register, the outputs of said control gates being connected to the inputs of said decoding network, the outputs of said control gates being inhibited by control signals generated by said control unit when the address stored in said addressing register exceed the number of addressable locations of said first auxiliary memory.

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EPB1 en. JPHB2 en. CAA en. DED1 en. ITB en. YUB en. Hierarchical priority branch handling for parallel execution in a parallel processor. Digital signal processor with multiway branching based on parallel evaluation of N threshold values followed by sequential evaluation of M. Controller for supplying multiplexed or non-multiplexed address signals to different types of dynamnic random access memories. Micro-code sequencer with branch-taken and branch-not-taken micro-code vectors sharing common address to eliminate taken branch penalties.

Expanded functionality of processor operations within a fixed width instruction encoding. USB1 en.